1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a flash memory having a variable range, in which erasing or writing is performed.
2. Description of the Background Art
A flash memory is a kind of nonvolatile memories (EEPROM) allowing electrical rewriting, and particularly is a memory allowing collective erasing of multiple memory cells. Flash memories of large capacities have been available in recent years, and in many case, such flash memories have employed a block erasing manner, in which a memory array is divided into a plurality of blocks, and collective erasing is performed block by block.
FIG. 22 is a flowchart illustrating an operation of block erasing of a conventional flash memory.
FIG. 23 is a circuit diagram of a memory block.
For the sake of simplicity, FIG. 23 shows memory cells arranged in four rows and four columns in the memory block. Each memory cell includes a memory transistor, which can nonvolatilely store data by changing its threshold voltage. The memory transistor has a floating gate, and electrons are injected into the floating gate or are pulled out from the floating gate so that the threshold voltage changes. The memory transistor thus configured will be simply referred to as a “memory cell” hereinafter.
Referring to FIGS. 22 and 23, when the block erasing starts, pre-erase writing is performed in a step S501.
FIG. 24 shows a distribution of threshold voltages of the memory cells exhibited after the pre-erase writing.
Before the erasing, some of the memory cells in the memory block usually have data of “1”, and the others have data of “0”. Therefore, if the erasing operation is performed in this state, many memory cells are over-erased. When the pre-erase writing is performed, the distribution of threshold voltages of the memory cells in the memory block shifts toward a high-voltage side, as shown in FIG. 24.
After step S501 in FIG. 22, operations are performed in subsequent steps S502 and S503 to set the memory block to a first erased state. More specifically, reading from the respective memory cells is performed while changing the row and column addresses, and erase verify 1 in step S502 is performed to determine whether the memory cell is in the erased state or not.
Every time it is determined in step S502 that the memory cell is not in the erased state, an erase pulse is applied collectively to the memory block at a time in step S503.
For the sake of distinction, the erase pulse, which is applied in step S503 for achieving the first erased state, will be referred to as an “erase pulse 1” in the following description, and a pulse applied in a later step S507 for achieving a second erased state will be referred to as an “erase pulse 2”, hereinafter. Also, in connection with the erase pulses 1 and 2, verify for verifying the first erased state will be referred to as “erase verify 1”, and verify for verifying the second erased state will be referred to as “erase verify 2”, hereinafter.
As shown in FIG. 23, application of the erase pulse in step S503 is performed by setting predetermined voltages on word lines, bit lines and a source line. More specifically, all word lines WL0–WL3 are set to a negative voltage, e.g., of −10 V., and all bit lines BL0–BL3 are set to an open state. Also, A source line SL is set to a positive voltage, e.g., of +10 V. By setting the voltages as described above, the erase pulse, which can act to lower the threshold voltage, is applied collectively to all the memory cells in the memory block at a time.
FIG. 25 shows voltages applied to a memory transistor when the erase pulse is applied.
Referring to FIG. 25, a negative voltage, e.g., of −10 V is applied to a control gate connected to a word line. A positive voltage, e.g., of +10 V is applied to a P-well and a source. This source is connected to source line SL. A drain of the memory transistor is open. This drain is connected to a bit line. An N-well, in which a P-well is formed, is set to a positive voltage, e.g., of +10 V. Since the erase pulse is applied, electrons are pulled out from the floating gate by a tunneling phenomenon so that a threshold voltage Vth lowers.
FIG. 26 shows a distribution of the threshold voltages exhibited after application of the erase pulse 1.
Referring to FIGS. 22 and 26, after the erasing operation is completed in steps S502 and S503, the distribution of threshold voltages of the memory cells in the memory block is located in a region lower than a verify voltage Vth1. However, immediately after passing the erase verify 1 in step S502, over-erasing may occur, and thus a lower end of the threshold voltage distribution may enter a region of the threshold voltage lower than 0 V. Therefore, processing of soft collective write verify and application of a soft collective write pulse are performed in steps S504 and S505, respectively. The write pulse, which is applied in step S505 and is weaker than that in an ordinary write operation, is referred to as the soft collective write pulse.
FIG. 27 shows a state of voltages applied in the memory cell when the soft collective write pulse is applied.
Referring to FIG. 27, a positive voltage, e.g., of +10 V is placed on the control gate connected to the word line. A negative voltage, e.g., of −5 V is placed on the source connected to source line SL and the P-well, in which the memory transistor is formed. The drain connected to the bit line is open. A power supply voltage Vdd is placed on the N-well located under the P-well. The tunneling phenomenon injects electrons into the floating gate to raise threshold voltage Vth.
FIG. 28 shows a distribution of the threshold voltages exhibited immediately after the soft collective write verify is completed.
Referring to FIGS. 22 and 28, the soft collective write pulse is applied collectively to the memory block in step S505. This shifts a lower limit value of the threshold voltage distribution of the memory cell. A soft write pulse is applied collectively to all the memory cells in the memory block at a time so that the lower limit value of the threshold voltage distribution of the memory cells may be equal to or higher than a verify voltage Vth2. When the lower limit value of the threshold voltage distribution of the memory cells becomes equal to or higher than verify voltage Vth2, the soft collective write verify in step S504 is passed.
When the soft collective write verify in step S504 is passed, some bits may exhibit a distribution protruding beyond the upper limit of the threshold voltage distribution. For returning such protruding threshold voltages of the bits to the erased state, the erase pulse 2 is applied again to the memory block in steps S506 and S507.
Application of the erase pulse 2 is repeated in steps S506 and S507 until the whole distribution of threshold voltages of the memory cells becomes equal to or lower than a predetermined upper limit voltage Vth3. This application of the erase pulse 2 in step S507 is performed by applying the pulse to all the memory cells in the block at a time, similarly to step S503.
FIG. 29 shows a distribution of the threshold voltages exhibited after completion of the erase verify 2 in step S506.
By applying the erase pulse 2 after the soft collective writing, the threshold voltage not exceeding verify voltage Vth3 is achieved even for the bit previously exhibiting the protruded portion of the distribution.
When the erase verify 2 is finally completed in step S506, over-erase recovery is effected on the over-erased memory cells on a bit-by-bit basis in subsequent steps S508 and S509.
FIG. 30 shows a distribution of threshold voltages of the memory cells exhibited after the over-erase verify in step S508 is completed.
When it is determined from the reading in step S508 that the memory is over-erased, a write pulse is applied to one of the memory cells, which are determined as the over-erased memory cells, in step S509. As a result of repeating of steps S508 and S509, the write pulse is applied only to the memory cells having the threshold voltages lower than a verify voltage Vth4, and the threshold voltage of the memory cell supplied with the write pulse shifts toward a high-voltage side.
By performing the processing in accordance with the flow illustrated in FIG. 22, the distribution of threshold voltages of the memory cells in the memory block are kept between the set voltage values of the lower and upper limits of the threshold voltage. Thereby, the collective block erasing operation is completed.
As described above, even when the same write pulse and the same erase pulse are applied, the threshold voltages of the memory cells exhibit a wide distribution due to variations in characteristics of the memory cells. Therefore, collective application of the write pulse and erase pulse to the block is repeated multiple times while changing the pulse intensity, and finally the writing is effected on the over-erased memory cells bit by bit. In first and subsequent some operations, the pulse is applied collectively to all the memory cells for the purpose of reducing the total times of required pulse application. If the writing were effected bit by bit even in the first and subsequent some operations, this would increase the times of pulse application, and would increase the erasing time.
As a prior art related to the collective erasing of the nonvolatile semiconductor memory device, Japanese Patent Laying-Open No. 03-105795 has disclosed a technique for achieving various types of partial erasing including collective erasing of the memory array.
In a prior art, application of the erase pulse 2 after the soft collective writing is performed a block at a time. More specifically, the erase pulse 2 is applied every time the erase verify is failed. The erase verify is performed to determine the pass/fail of data by reading data of one, eight or sixteen bit(s) at a time while successively incrementing both the row and column addresses. For example, in the case of the memory block formed of 16 memory cells shown in FIG. 23, reading from the memory cell is performed a memory cell at a time, and the determination of pass/fail is performed a memory cell at a time.
Therefore, even when a region corresponding to a “small” row address and a “small” column address passes the verify, the erase pulse 2 will be applied to this region if it fails the verify of a region corresponding to a higher address, at which the verify is performed later.
Consequently, the region, which already passed the verify, will be excessively supplied with the erase pulse until the threshold voltage of all the memory cells in the block to be erased lowers to or below the erase verify voltage. Thereby, the threshold voltages of the memory cells, which excessively received the erase pulse, become lower than the lower limit of the allowable distribution so that the number of over-erased memory cells increases. Since the memory cells, which are to be processed by the over-erase recovery writing, increase in number, the erase time increases.